1. Field of the Invention
The invention relates in general to a digital decimation filter which includes a multiplexer that produces two outputs in which the first signal path receives the even-numbered signal values of an input signal supplied to the multiplexer and the second signal path receives the odd-numbered signal values from the multiplexer. Multipliers weigh the signal values with a plurality of binary filter coefficients and include first adders arranged in a first iterative circuit for adding weighted signal values and every multiplier is divided into a plurality of partial product stages corresponding in number with the number of binary filter coefficients and each of the partial product stages weights the signal based on one filter coefficient bit.
2. Description of the Prior Art
A decimation filter having fixed coefficients is described in the article "MOS Digital Filter Design" by W. Ulbrich pages 236 through 271 of the book entitled "Design of MOS VLSI Circuits for Telecommunications", edited by Y. Tsividis and P. Antognetti, Prentice-Hall, Incorporated, 1985, New Jersey of which publication is hereby incorporated by reference. Particular relevant disclosure material is included in FIGS. 9a and 10 and the description on pages 251 and 252 of a decimation filter. The known decimation filter is utilized in circuits for a digital signal processing so as to halve the sampling rate of the signals which are to be processed. The multiplexer arranged at the input of the filter is driven with a sampling rate of the digitized signal values which are supplied to it and the signal path connected to the outputs and the subcircuits of the filter connected to such signal paths are operated at half the sampling rate of the input signal.